1. Field of the Invention
The present invention relates to a semiconductor memory controller which controls the operation of a plurality of semiconductor memories in a device such as an IC card.
2. Description of Related Art
FIG. 11 is a circuitry block diagram showing a conventional semiconductor memory controller. In the figure, a reference numeral 1 denotes an address buffer circuit; 2a an even number byte address decoder circuit; 2b an odd number byte address decoder circuit; and 3 a write signal control circuit for controlling a write enable signal line (WE) 12 and a write protect signal line (WP) 16. In addition, a reference numeral 4 denotes an address input bus (AD) on which an address signal is supplied; 5 a reset signal line (RST); 6 to 9 address decoder signal input lines; and 10 and 11 denote first and second chip select enable signal lines (CSE1 and CSE2), respectively. Further, a reference numeral 13 denotes an address output bus for outputting an address signal; 14a a group of even number byte address decoder output lines including 8 output lines; 14b a group of odd number byte address decoder output lines including 8 output lines, similarly; 15 a write enable signal output line; and 17 a write protect signal output line.
An input side is on the left side of FIG. 11 and external signals are inputted to the signal lines denoted by the reference numerals 4 to 12 and 16. The signal lines denoted by the reference numerals 13, 14a, 14b and 15 on the right side of FIG. 11 are of the output side and a plurality of semiconductor memories not shown are connected to these output signal lines to be controlled. The write protect signal output line 17 is used as a signal for indicating the status of the controller. It should be noted that a signal line is indicated with the same reference numeral as that of a signal transferred on the signal line in the following description.
The controller is of a byte address system and can selectively perform one of an N-bit operation and a 2N-bit operation. 16 (8.times.2) semiconductor memories (not shown) can be totally connected to the group 14a of even number byte address decoder output lines and the group 14b of odd number byte address decoder output lines. Each of the address decoder output lines is connected to, for example, a chip enable terminal of the semiconductor memory to set the connected memory in an active state by giving a signal of a predetermined level. A signal of the write enable signal output line 15 is connected to the write enable terminal of each of the semiconductor memories to set the semiconductor memories in a write enable state. The address output bus 13 is connected to the respective semiconductor memories to designate one address in the semiconductor memories.
The first and second chip select enable signals 10 and 11 are for switching the operation between the N-bit operation and the 2N-bit operation. The address decoder signals 6, 7 and 8 designate to which output lines of the address decoder output line groups 14a and 14b of the address decoder circuits 2a and 2b are to supply the enable signals, respectively. The address signal 4 further designate one address of each of the semiconductor memories. The address decoder signal input line 9 selects one of the odd number byte address decoder circuit 2a and the even number byte address decoder circuit 2b by switching for every byte in the N-bit operation. Thus, with respect to the address signal 4 and the address decoder signals 6 to 9, an address signal is formed in which the least significant bit is the address decoder signal 9, the address signal 4 are coupled thereto from the lower bits to the upper bits, then the address decoder signals 6, 7 and 8 are coupled thereto, and lastly the address decoder signal 8 is coupled thereto as the most significant bit. It should be noted that the two address decoder circuits 2a and 2b are operated in parallel in the 2N-bit operation.
FIG. 12 is a circuit diagram of the address bus buffer circuit 1 shown in FIG. 11. A reference numeral 4a denotes an address input line of the address input bus 4; 13a an address output line of the address output bus 13; 100 a buffer connected to the address input line 4a; 101 an inverter connected to the reset signal line 5; 102 an AND gate inputting the first and second chip select enable signals 10 and 11; 103 an OR gate connected to the output of the inverter 101 and the output of the AND gate 102 on the input side; and 104 an OR gate inputting the output the OR gate 103 and the output of the buffer 100. The circuit diagram shows only the construction for the one address input line 4a. The buffer 100 and the OR gate 104 are provided for each address input line 4a and the inverter 101, the AND gate 102 and the OR gate 103 are provided commonly for the address input lines 4a.
FIG. 13 is the operation mode table showing the operation of the even number byte address decoder circuit 2a and odd number byte address decoder circuit 2b shown in FIG. 11.
FIG. 14 is the circuit diagram of the write signal control circuit 3 shown in FIG. 11. A reference numeral 300 a buffer connected to the write enable signal input line 12; 301 an inverter connected to the reset signal line 5; 302 an AND gate to which the first and second chip select enable signals 10 and 11 are inputted; 303 an OR gate to which the output of the AND gate 302, the output of the inverter 301 and the write protect input signal 16 are inputted; 304 an OR gate to which the outputs of the OR gate 303 and the buffer are inputted; and 305 a buffer connected to the write protect signal output line 17.
Next, the operation will be described below. In this case the circuit is of negative logic.
The address bus buffer circuit 1 shown in FIG. 1 is a buffer circuit for the address input bus 4 and acts to achieve the baffer circuit and in addition controls the address input signal 4 to gate in accordance with the first and second chip select enable signals 10 and 11 and the reset signal 5.
As should be seen from FIG. 12, the address output signal 13a is set to the H level regardless of the address input signal 4a when the state in which the operation of the circuit is stopped, i.e., when there is established either one of the state in which the first and second chip select enable signal 10 and 11 are both in the H level, and the state in which the reset signal 5 is in the L level. This is because the address output bus 13 cannot be functioned when the operation of the controller is stopped. On the operation of the controller, i.e., when the reset signal 5 is in the H level, and when at least one of the first and second chip select enable signals 10 and 11 is in the L level, the address input signal 4a is supplied as the address output signal 13a.
Next, the even number byte address decoder circuit 2a and the odd number byte address decoder circuit 2b select one semiconductor memory or two semiconductor memories at a time in accordance with the reset signal 5, the address decoder input signals 6 to 9, the first and second chip select enable signals 10 and 11 and operate in accordance with the operation table shown in FIG. 13. As seen from FIG. 13, in the same manner as in the address buffer circuit 1, all signals on the decoder output line group 14a and 14b, each of which includes 8 output lines) are set in the H level when there is established either one of the state in which both the first and second chip select enable signals 10 and 11 are set in the H level and the state in which the reset signal 5 is set in the L level.
When the reset signal 5 is set in the H level, the controller is in the operation state and when the first enable signal 10 is set in the L level and the second enable signal 11 is set in the H level, the N-bit operation is performed. In this N-bit operation, when the address decoder signal 9 as the even number byte or the odd number byte select signal is set to the L level, one of the decoder output line group 14a of the even number byte address decoder circuit 2a is set the L level and when the address decoder signal 9 is set in the H level, one of the decoder output line group 14b of the odd number byte address decoder circuit 2b is set in the L level. In this manner, the semiconductor memory connected to the decoder output line of the L level is selected. Which signal line of the decoder output line groups 14a and 14b of the decoder circuits 2a and 2b is selected is determined based on 3 bits of the address decoder signals 6 to 8.
On the other hand, the 2N-bit operation is performed when the reset signal 5 is set in the H level and when both the first and second enable signal 10 and 11 are set in the L level. In this 2N-bit operation, one of each of the decoder output line groups 14a and 14b of the decoder circuits 2a and 2b is set in the L level in accordance with the address decoder signals 6 to 8 so that two semiconductor memories are selected at a time.
The write signal control circuit 3 is a circuit for controlling the write operation of data into a semiconductor memory by connecting the write enable output signal 15 to the write enable terminal of the semiconductor memory. As shown in FIG. 14, in the write signal control circuit 3, the write enable output signal 15 is set in the H level regardless of the write enable input signal 12 when the write protect input signal 16 is set in the H level in addition to when the controller is in the operation stopping state in which the first and second enable signals 10 and 11 are both set in the H level or the reset signal 5 is set in the L level as described above. The write enable output signal 15 is supplied in accordance with the write enable input signal 12 when at least one of the first and second enable signals 10 and 11 is set in the L level, the reset signal 5 is set in the H level, and the write protect input signal 16 is set in the L level, It should be noted that the write protect input signal 16 is always outputted as it is as the write protect output signal 17 regardless of the set level of another signal.
The conventional semiconductor memory controller is constructed as described above and has the following problems.
(1) First, in the conventional controller, the problem is caused in which if the circuits are constructed to have the CMOS structure, a "pass through" current flows in these circuit so that the power consumption increases unnecessarily when the signals of the input lines (including the bus) denoted with the reference numerals 4 to 12 and 16 in FIG. 11 change into an intermediate level between the L level and the H level.
(2) Next, in the convention controller, because the address bus buffer circuit 1 is designed to hold all the output signals 13 in the H level when the controller is not in the operation state (in the backup state), current is unnecessarily supplied in the operation stopping state in a case where there is connected an non-volatile semiconductor memory such as ROM which does not need the power supply. Therefore, there is caused another problem that the power is consumed unnecessarily when various types of semiconductor memories such as ROM and RAM different in signal levels to be supplied from each other are mixedly connected. In addition, in a case where the signal is fixed to the H level in the backup state, the problem on the change of signal level is cased so that the pass through current problem is also caused.
(3) Next, in the conventional controller, there is caused another problem that although the even number and odd number byte address decoder circuits 2a and 2b can individually control the N-bit operation semiconductor memory and the 2N-bit operation semiconductor memories such that they can be switched, the circuits 2a and 2b cannot control the semiconductor memories in the state in which the N-bit operation state and the 2N-bit operation state are mixedly present.
(4) Further, in the conventional controller, there is caused still another problem that because all the address space (memory space) is divided in units of a predetermined area unit in accordance with the address decoder output signal groups 14a and 14b of the even number and odd number byte address decoder circuits 2a and 2b, the divided area cannot be divided into the further small areas.
(5) Furthermore, in the conventional controller, the signals such as the output signals 14a and 14b of the address decoder circuits 2a and 2b and the write enable output signal 15 of the write signal control circuit 3 are all set in the H level forcedly when the controller is in the operation stopping state (in the backup state) because the controller is of a negative logic circuit). However, the above output signals is preferably set in the L level (GND level) because the power is not consumed unnecessarily in a case of the non-volatile semiconductor memory such as ROM which does not require the power supply in the backup state. Thus, there is caused in the conventional controller further another problem that the signal levels of the output signals of the address decoder circuits 2a and 2b and the write signal control circuit 3 cannot changed based on the type of the semiconductor memory connected thereto.